1. Field of the Invention
The present invention relates to a differential amplifier.
2. Description of Related Art
Presently, a differential amplifier is used for a differential input buffer in a receiving circuit of a high-speed interface such as USB 2.0. Japanese Unexamined Patent Application Publication No. 3-85817 discloses a technique of such a differential amplifier as prior art. Meanwhile, in a semiconductor device equipped with the differential amplifier, a power down technique that stops an operating current when the differential amplifier stops operating is generally used for reducing power consumption. FIGS. 12 and 13 show configurations of differential amplifiers 1 and 2 according to related art. The differential amplifiers 1 and 2 are added a switching circuit for reducing power consumption in the configuration the circuit disclosed in Japanese Unexamined Patent Application Publication No. 3-85817. Note that the differential amplifiers 1 and 2 are composed of MOS transistors of opposite conductivity types.
As shown in FIG. 12, the differential amplifier 1 includes PMOS transistors MP1 to MP4 and a power-down switch circuit PDSW1.
The source of the PMOS transistor MP3 is connected to a power-supply voltage terminal VDD, the drain of the PMOS transistor MP3 is connected to an output terminal OT, and the gate of the PMOS transistor MP3 is connected to an input terminal IB. The source of the PMOS transistor MP4 is connected to the power-supply voltage terminal VDD, the drain of the PMOS transistor MP4 is connected to an output terminal OB, and the gate of the PMOS transistor MP4 is connected to an input terminal IT. The source of the PMOS transistor MP1 is connected to the output terminal OT, the drain of the PMOS transistor MP1 is connected to a node N1, and the gate of the PMOS transistor MP1 is connected to the input terminal IT. The source of the PMOS transistor MP2 is connected to the output terminal OB, the drain of the PMOS transistor MP2 is connected to a node N2, and the gate of the PMOS transistor MP2 is connected to the input terminal IB.
The power-down switch circuit PDSW1 includes NMOS transistors MN11 and MN12. The drain of the NMOS transistor MN11 is connected to the node N1, and the source of the NMOS transistor MN11 is connected to a ground voltage terminal GND. The drain of the NMOS transistor MN12 is connected to the node N2, and the source of the NMOS transistor MN12 is connected to the ground voltage terminal GND. A power down signal PDB is input to the gates of the NMOS transistors MN11 and MN12. When the power down signal PDB is high level, the differential amplifier 1 is in a normal operation state. Meanwhile, when the power down signal PDB is low level, the differential amplifier 1 is in a power down state (stand-by state).
As shown in FIG. 13, the differential amplifier 2 includes NMOS transistors MN1 to MN4 and a power-down switch circuit PDSW2. The source of the NMOS transistor MN1 is connected to the ground voltage terminal GND, the drain of the NMOS transistor MN1 is connected to the output terminal OT, and the gate of the NMOS transistor MN1 is connected to the input terminal IT. The source of the NMOS transistor MN2 is connected to the ground voltage terminal GND, the drain of the NMOS transistor MN2 is connected to the output terminal OB, and the gate of the NMOS transistor MN2 is connected to the input terminal IB. The source of the NMOS transistor MN3 is connected to the output terminal OT, the drain of the NMOS transistor MN3 is connected to a node N3, and the gate of the NMOS transistor MN3 is connected to the input terminal IB. The source of the NMOS transistor MN4 is connected to the output terminal OB, the drain of the NMOS transistor MN4 is connected to a node N4, and the gate of the NMOS transistor MN4 is connected to the input terminal IT.
The power-down switch circuit PDSW2 includes PMOS transistors MP11 and MP12. The drain of the PMOS transistor MP11 is connected to the node N3, and the source of the PMOS transistor MP11 is connected to the power-supply voltage terminal VDD. The drain of the PMOS transistor MP12 is connected to the node N4, and the source of the PMOS transistor MP12 is connected to the power-supply voltage terminal VDD. A power down signal PDB is input to the gates of the PMOS transistors MP11 and MP12. When the power down signal PDB is low level, the differential amplifier 2 is in the normal operation state. Meanwhile, when the power down signal PDB is high level, the differential amplifier 2 is in the power down state (stand-by state).
For convenience of description, reference symbols “VDD” and “GND” represent a power-supply voltage and a ground voltage, respectively, and also represent terminal names. Further, for convenience of description, reference symbols “IT” and “IB” represent terminal names as well as names of signals input to the terminals. Furthermore, for convenience of description, reference symbols “OT” and “OB” represent terminal names as well as names of signals output from the terminals.
FIG. 14 shows a timing diagram illustrating operation of the differential amplifier 1. Referring to FIG. 14, before a time t1, the differential amplifier 1 is in the power down state because the power down signal PDB is low level. At the time t1, the power down signal PDB is high level. Thus, the differential amplifier 1 starts normal operation, and outputs the differential output signals OT and OB in response to the differential input signals IT and IB. At a time t2, the power down signal PDB becomes low level again. Accordingly, the differential amplifier 1 becomes the power down state again.
Note that the polarity of each signal in FIG. 14 is opposite to that shown in a timing diagram illustrating operation of the differential amplifier 2. Except for this point, the basic operation of the differential amplifier 2 is similar to that of the differential amplifier 1. Therefore, explanation of the operation thereof is omitted here.